查詢教學大綱與進度

教學大綱與進度

課程基本資料：

學年期課號課程名稱階段學分時數修教師班級人撤備註

112-1 319109 數位系統 1 3.0 3 ★ 劉俊麟電機三甲 44 0 　

學年期	課號	課程名稱	階段	學分	時數	修	教師	班級	人	撤	備註
112-1	319109	數位系統	1	3.0	3	★	劉俊麟	電機三甲	44	0

教學大綱與進度：

教師姓名劉俊麟　教師諮商時間(Office Hours)

Email junlin@mail.ntut.edu.tw

最後更新時間 2023-05-29 00:16:30

課程大綱最佳化組合邏輯之演算法，可規劃邏輯元件，組合邏輯之VLSI設計，使用MSI與標準電路元件設計多層邏輯，使用閘陣列設計，循序邏輯之元件，循序邏輯之分析與合成，VLSI之設計與測試技巧，各種CALD軟體工具介紹。 1.Algorithms for Optimization of combirational logic 2.VLSI realizations of combination logic 3.Multilevel logic using complex parts and cells. 4.Components of sequential systems 5.Synthesis of clock-mode sequential circuits.

課程進度 Week1: Review of Logic Design Fundamentals (1/3) Week2: Review of Logic Design Fundamentals (2/3) Week3: Review of Logic Design Fundamentals (3/3) Week4: Introduction to Verilog (1/3) Week5: Introduction to Verilog (2/3) Week6: Introduction to Verilog (3/3) Week7: Verilog Simulation and Testbench (1/2) Week8: Verilog Simulation and Testbench (2/2) Week9: Midterm Examination week10: Introduction to PLD Week11: Design Examples (1/2) Week12: Design Examples (2/2) Week13: Design Examples (3/3) Week14: SM Charts and Microprogramming (1/2) Week15: SM Charts and Microprogramming (2/2) Week16: Designing with FPGA (1/2) Week17: Designing with FPGA (2/2) Week18: Final Examination

評量方式與標準 Attendance: 10% (five roll calls) In-class Participation: 5% Assignments: 25% Midterm Exam. : 30% Final Exam.：30%

使用教材、參考書目或其他 【遵守智慧財產權觀念，請使用正版教科書，不得使用非法影印教科書】

使用外文原文書：是
Textbook: Charles Roth, Lizy Kurian John, and Byeong Kil Lee, Digital Systems Design Using Verilog, International Edition, 2016, Cengage Learning Reference books: 1. Logic and Computer Design Fundamentals, Morris Mano, Charles R. Kime, Tom Martin, 2016, Pearson 2. 數位系統設計 - 原理、實務與應用, 第5版，林銘波編著

課程諮詢管道 1. Teacher office hours for 112-1 @綜科館215:
Tue. 10:10 ~ 12:1, Wed. 15:10 ~ 17:10
2. Please mail junlin@ntut.edu.tw in advance to reserve the time for face-to-face or online curricular consultation.

課程對應SDGs指標

備註

教師姓名	劉俊麟　教師諮商時間(Office Hours)
Email	junlin@mail.ntut.edu.tw
最後更新時間	2023-05-29 00:16:30
課程大綱	最佳化組合邏輯之演算法，可規劃邏輯元件，組合邏輯之VLSI設計，使用MSI與標準電路元件設計多層邏輯，使用閘陣列設計，循序邏輯之元件，循序邏輯之分析與合成，VLSI之設計與測試技巧，各種CALD軟體工具介紹。 1.Algorithms for Optimization of combirational logic 2.VLSI realizations of combination logic 3.Multilevel logic using complex parts and cells. 4.Components of sequential systems 5.Synthesis of clock-mode sequential circuits.
課程進度	Week1: Review of Logic Design Fundamentals (1/3) Week2: Review of Logic Design Fundamentals (2/3) Week3: Review of Logic Design Fundamentals (3/3) Week4: Introduction to Verilog (1/3) Week5: Introduction to Verilog (2/3) Week6: Introduction to Verilog (3/3) Week7: Verilog Simulation and Testbench (1/2) Week8: Verilog Simulation and Testbench (2/2) Week9: Midterm Examination week10: Introduction to PLD Week11: Design Examples (1/2) Week12: Design Examples (2/2) Week13: Design Examples (3/3) Week14: SM Charts and Microprogramming (1/2) Week15: SM Charts and Microprogramming (2/2) Week16: Designing with FPGA (1/2) Week17: Designing with FPGA (2/2) Week18: Final Examination
評量方式與標準	Attendance: 10% (five roll calls) In-class Participation: 5% Assignments: 25% Midterm Exam. : 30% Final Exam.：30%
使用教材、參考書目或其他	【遵守智慧財產權觀念，請使用正版教科書，不得使用非法影印教科書】使用外文原文書：是 Textbook: Charles Roth, Lizy Kurian John, and Byeong Kil Lee, Digital Systems Design Using Verilog, International Edition, 2016, Cengage Learning Reference books: 1. Logic and Computer Design Fundamentals, Morris Mano, Charles R. Kime, Tom Martin, 2016, Pearson 2. 數位系統設計 - 原理、實務與應用, 第5版，林銘波編著
課程諮詢管道	1. Teacher office hours for 112-1 @綜科館215: Tue. 10:10 ~ 12:1, Wed. 15:10 ~ 17:10 2. Please mail junlin@ntut.edu.tw in advance to reserve the time for face-to-face or online curricular consultation.
課程對應SDGs指標
備註