查詢教學大綱與進度

教學大綱與進度

課程基本資料：

學年期課號課程名稱階段學分時數修教師班級人撤備註

111-1 304583 數位系統 1 3.0 3 ★ 劉俊麟電機三丙 48 1 ◎

學年期	課號	課程名稱	階段	學分	時數	修	教師	班級	人	撤	備註
111-1	304583	數位系統	1	3.0	3	★	劉俊麟	電機三丙	48	1	◎

教學大綱與進度：

教師姓名劉俊麟　教師諮商時間(Office Hours)

Email junlin@mail.ntut.edu.tw

最後更新時間 2022-09-14 13:00:10

課程大綱最佳化組合邏輯之演算法，可規劃邏輯元件，組合邏輯之VLSI設計，使用MSI與標準電路元件設計多層邏輯，使用閘陣列設計，循序邏輯之元件，循序邏輯之分析與合成，VLSI之設計與測試技巧，各種CALD軟體工具介紹。 1.Algorithms for Optimization of combirational logic 2.VLSI realizations of combination logic 3.Multilevel logic using complex parts and cells. 4.Components of sequential systems 5.Synthesis of clock-mode sequential circuits.

課程進度 Week1: Review of Logic Design Fundamentals (1/2) Week2: Review of Logic Design Fundamentals (2/2) Week3: Introduction to Verilog (1/3) Week4: Introduction to Verilog (2/3) Week5: Introduction to Verilog (3/3) Week6: Introduction to PLD Week7: Design Examples (1/2) Week8: Design Examples (2/2) Week9: Midterm Exam. Week10: SM Charts and Microprogramming Week11: Designing with FPGA (1/2) Week12: Designing with FPGA (2/2) Week13: Floating-point Arithmetic Week14: Additional Topics in Verilog (1/2) Week15: Additional Topics in Verilog (2/2) Week16: Design of a RISC Microprocessor Week17: Hardware Testing and Design for Testability Week18: Final Exam.

評量方式與標準 Attendance: 10% (five roll calls)， Group participation: 10% Assignments: 25%， Midterm Exam. : 25%， Final Exam.：30%

使用教材、參考書目或其他 【遵守智慧財產權觀念，請使用正版教科書，不得使用非法影印教科書】

使用外文原文書：是
Textbook: Charles Roth, Lizy Kurian John, and Byeong Kil Lee, Digital Systems Design Using Verilog, International Edition, 2016, Cengage Learning (Ref. book: 數位系統設計 - 原理、實務與應用, 第5版，林銘波編著)

課程諮詢管道 (1) Teacher office hours @綜科館215:
Tue. 14:00 ~ 15:00, Wed. 10:00 ~ 11:00, Fri. 13:00 ~ 15:00

(2) or email to junlin@ntut.edu.tw for arranging other online or face-to-face curricular consultation

備註
(1) This course will be taught in English

(2) During the severe epidemic period, online classes will be adopted using MS Teams software to facilitate the teaching and discussion.

教師姓名	劉俊麟　教師諮商時間(Office Hours)
Email	junlin@mail.ntut.edu.tw
最後更新時間	2022-09-14 13:00:10
課程大綱	最佳化組合邏輯之演算法，可規劃邏輯元件，組合邏輯之VLSI設計，使用MSI與標準電路元件設計多層邏輯，使用閘陣列設計，循序邏輯之元件，循序邏輯之分析與合成，VLSI之設計與測試技巧，各種CALD軟體工具介紹。 1.Algorithms for Optimization of combirational logic 2.VLSI realizations of combination logic 3.Multilevel logic using complex parts and cells. 4.Components of sequential systems 5.Synthesis of clock-mode sequential circuits.
課程進度	Week1: Review of Logic Design Fundamentals (1/2) Week2: Review of Logic Design Fundamentals (2/2) Week3: Introduction to Verilog (1/3) Week4: Introduction to Verilog (2/3) Week5: Introduction to Verilog (3/3) Week6: Introduction to PLD Week7: Design Examples (1/2) Week8: Design Examples (2/2) Week9: Midterm Exam. Week10: SM Charts and Microprogramming Week11: Designing with FPGA (1/2) Week12: Designing with FPGA (2/2) Week13: Floating-point Arithmetic Week14: Additional Topics in Verilog (1/2) Week15: Additional Topics in Verilog (2/2) Week16: Design of a RISC Microprocessor Week17: Hardware Testing and Design for Testability Week18: Final Exam.
評量方式與標準	Attendance: 10% (five roll calls)， Group participation: 10% Assignments: 25%， Midterm Exam. : 25%， Final Exam.：30%
使用教材、參考書目或其他	【遵守智慧財產權觀念，請使用正版教科書，不得使用非法影印教科書】使用外文原文書：是 Textbook: Charles Roth, Lizy Kurian John, and Byeong Kil Lee, Digital Systems Design Using Verilog, International Edition, 2016, Cengage Learning (Ref. book: 數位系統設計 - 原理、實務與應用, 第5版，林銘波編著)
課程諮詢管道	(1) Teacher office hours @綜科館215: Tue. 14:00 ~ 15:00, Wed. 10:00 ~ 11:00, Fri. 13:00 ~ 15:00 (2) or email to junlin@ntut.edu.tw for arranging other online or face-to-face curricular consultation
備註	(1) This course will be taught in English (2) During the severe epidemic period, online classes will be adopted using MS Teams software to facilitate the teaching and discussion.