查詢教學大綱與進度

教學大綱與進度

課程基本資料：

學年期課號課程名稱階段學分時數修教師班級人撤備註

110-1 294458 電腦輔助積體電路系統設計實務 1 3.0 3 ★ 宋國明電機所
電資外生所 14 0 ◎

學年期	課號	課程名稱	階段	學分	時數	修	教師	班級	人	撤	備註
110-1	294458	電腦輔助積體電路系統設計實務	1	3.0	3	★	宋國明	電機所電資外生所	14	0	◎

教學大綱與進度：

教師姓名宋國明

Email gmsung@ntut.edu.tw

最後更新時間 2021-09-21 12:04:57

課程大綱本課程希望協助學生瞭解如何以標準積體電路系統設計流程來設計超大型積體電路系統，旨在採用多種數位與類比電腦輔助設計軟體來訓練學生，使其能熟悉並使用超大型積體電路系統的設計軟體，培育學生具備超大型積體電路系統設計實務與經驗。本課程的主要內容包括：1.超大型積體電路簡介；2.晶片製程介紹；3.MOSFET元件；4. MOSFET走線；5.Hspice軟體介紹；6. Hspice電路模擬；7.類比電路佈局與實作；8.Verilog HDL(硬體描述語言)；9.電路合成；10.自動測試圖樣產生；11.時脈靜態分析；12.電路佈局與佈線；13.DRC與LVS檢測；14.寄生參數萃取與佈局後模擬；15.設計功能驗證16. 設計方案報告 Students will learn how to design VLSI circuits and systems based on a standard VLSI system design flow, where various electronic design automation (EDA) tools will be used extensively in the semester. Those EDA tools includes analog and digital circuits and systems. The main purpose of this course includes the following: 1. VLSI Introduction. 2. Manufacturing Process. 3. MOSFET Devices. 4. MOSFET Wires. 5. Hspice Software. 6. Hspice Simulation. 7. Analog IC Layout and Practice. 8. Verilog-HDL. 9. Synthesis. 10. Design for Testability and Automatic Test Pattern Generation. 11. Static Timing Analysis. 12. Placement and Routing. 13. Design Rule Check, Layout Versus Schematic. 14. Layout Parasitic Extraction and Simulation. 15. Design Verification. 16. Project Presentation.

課程進度 Week 1 VLSI Introduction. Week 2 Manufacturing Process. Week 3 MOSFET Devices. Week 4 MOSFET Wires. Week 5 Hspice Software. Week 6 Hspice Simulation. Week 7 Hspice Examples Week 8 Analog IC Layout and Practice. Week 9 Verilog-HDL. Week 10 Synthesis. Week 11 Design for Testability and Automatic Test Pattern Generation. Week 12 Static Timing Analysis. Week 13 Placement and Routing. Week 14 Design Rule Check, Layout Versus Schematic. Week 15 Layout Parasitic Extraction and Simulation. Week 16 Smith Chart Simulation Week 17 ADS Software Week 18 ADS Examples

評量方式與標準 (1). General Performance 20%. (2). Homework 40%. (3). Midterm exam 30% (Open book). (3). Final Report 10%.

使用教材、參考書目或其他 【遵守智慧財產權觀念，請使用正版教科書，不得使用非法影印教科書】

使用外文原文書：是
Neil H. E. Weste and David Harris, “CMOS VLSI Design－A Circuit and System Perspective,”Third Edition, 2005. 偉明圖書有限公司 (www.wmbook.com.tw, TEL：2363-8586, 2363-6567, ISBN：0-321-14901-7)

課程諮詢管道 The extension number is 2121 and the location is Integrated Technology Complex Rm317.

備註 ●上課方式：遠距上課

●評量方式：
The mid-term and final exams will be proceeded according to the teaching method.
●補充說明資訊：
The extension number is 2190 for TA at the same building and room.

教師姓名	宋國明
Email	gmsung@ntut.edu.tw
最後更新時間	2021-09-21 12:04:57
課程大綱	本課程希望協助學生瞭解如何以標準積體電路系統設計流程來設計超大型積體電路系統，旨在採用多種數位與類比電腦輔助設計軟體來訓練學生，使其能熟悉並使用超大型積體電路系統的設計軟體，培育學生具備超大型積體電路系統設計實務與經驗。本課程的主要內容包括：1.超大型積體電路簡介；2.晶片製程介紹；3.MOSFET元件；4. MOSFET走線；5.Hspice軟體介紹；6. Hspice電路模擬；7.類比電路佈局與實作；8.Verilog HDL(硬體描述語言)；9.電路合成；10.自動測試圖樣產生；11.時脈靜態分析；12.電路佈局與佈線；13.DRC與LVS檢測；14.寄生參數萃取與佈局後模擬；15.設計功能驗證16. 設計方案報告 Students will learn how to design VLSI circuits and systems based on a standard VLSI system design flow, where various electronic design automation (EDA) tools will be used extensively in the semester. Those EDA tools includes analog and digital circuits and systems. The main purpose of this course includes the following: 1. VLSI Introduction. 2. Manufacturing Process. 3. MOSFET Devices. 4. MOSFET Wires. 5. Hspice Software. 6. Hspice Simulation. 7. Analog IC Layout and Practice. 8. Verilog-HDL. 9. Synthesis. 10. Design for Testability and Automatic Test Pattern Generation. 11. Static Timing Analysis. 12. Placement and Routing. 13. Design Rule Check, Layout Versus Schematic. 14. Layout Parasitic Extraction and Simulation. 15. Design Verification. 16. Project Presentation.
課程進度	Week 1 VLSI Introduction. Week 2 Manufacturing Process. Week 3 MOSFET Devices. Week 4 MOSFET Wires. Week 5 Hspice Software. Week 6 Hspice Simulation. Week 7 Hspice Examples Week 8 Analog IC Layout and Practice. Week 9 Verilog-HDL. Week 10 Synthesis. Week 11 Design for Testability and Automatic Test Pattern Generation. Week 12 Static Timing Analysis. Week 13 Placement and Routing. Week 14 Design Rule Check, Layout Versus Schematic. Week 15 Layout Parasitic Extraction and Simulation. Week 16 Smith Chart Simulation Week 17 ADS Software Week 18 ADS Examples
評量方式與標準	(1). General Performance 20%. (2). Homework 40%. (3). Midterm exam 30% (Open book). (3). Final Report 10%.
使用教材、參考書目或其他	【遵守智慧財產權觀念，請使用正版教科書，不得使用非法影印教科書】使用外文原文書：是 Neil H. E. Weste and David Harris, “CMOS VLSI Design－A Circuit and System Perspective,”Third Edition, 2005. 偉明圖書有限公司 (www.wmbook.com.tw, TEL：2363-8586, 2363-6567, ISBN：0-321-14901-7)
課程諮詢管道	The extension number is 2121 and the location is Integrated Technology Complex Rm317.
備註	●上課方式：遠距上課 ●評量方式： The mid-term and final exams will be proceeded according to the teaching method. ●補充說明資訊： The extension number is 2190 for TA at the same building and room.