教學大綱與進度
課程基本資料:
學年期
課號
課程名稱
階段
學分
時數
修
教師
班級
人
撤
備註
108-1
262690
數位邏輯
1
3.0
3
▲
吳昭正
電機一乙
48
0
教學大綱與進度:
教師姓名
吳昭正
Email
ccwu@ntut.edu.tw
最後更新時間
2019-05-22 15:16:39
課程大綱
布林代數與邏輯閘,組合邏輯,算術演算邏輯,同步循序邏 輯,演繹狀態機,非同步循序邏輯。
課程進度
Week 1. Introduction Week 2. Boolean Algebra & Logical Gates (I) Week 3. Boolean Algebra & Logical Gates (II) Week 4. Minterm and Maxterm Expansions Week 5. Karnaugh Maps Week 6. Quine-McClusky Method Week 7. Multi-Level Gate Circuits Week 8. Combinational Circuit Design and Simulation Using Gates Week 9. Midterm Exam Week 10. Multiplexers, Decoders, and Programmable Logic Devices Week 11. Latches and Flip-Flops (I) Week 12. Latches and Flip-Flops (II) Week 13. Registers and Counters (I) Week 14. Registers and Counters (II) Week 15. Analysis of Clocked Sequential Circuits Week 16. Derivation of State Graphs and Tables (I) Week 17. Derivation of State Graphs and Tables (II) Week 18. Final Exam
評量方式與標準
Homework exams 30% Midterm 30% Final 30% Attendance 10% Class Participation 10%
使用教材、參考書目或其他
【遵守智慧財產權觀念,請使用正版教科書,不得使用非法影印教科書】
使用外文原文書:是
Textbook: Fundamentals of Logic Design, 6th Edition, by Charles H. Roth, Jr. & Larry L. Kinney, Cengage, 2010
課程諮詢管道
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