查詢教學大綱與進度

教學大綱與進度

課程基本資料：

學年期課號課程名稱階段學分時數修教師班級人撤備註

112-2 327941 數位邏輯設計實習 1 1.0 3 ▲ 尤信程資工一 73 1 科1222

學年期	課號	課程名稱	階段	學分	時數	修	教師	班級	人	撤	備註
112-2	327941	數位邏輯設計實習	1	1.0	3	▲	尤信程	資工一	73	1	科1222

教學大綱與進度：

教師姓名尤信程　教師諮商時間(Office Hours)

Email scyou@ntut.edu.tw

最後更新時間 2024-03-11 10:47:51

課程大綱１.TTL，CMOS邏輯閘之特性實習２.組合邏輯電路設計實習含：算術電路，比較器，解碼器，編碼器，多工器，解多工器等３.序向邏輯電路設計與應用：正反器，計數器，記錄器，及移位暫存器等綜合應用４.FPGA設計規劃。

課程進度 Week 1 General announcement and lab administration Week 2 Lab 0: Use of lab equipment Week 3 Lab 1: TTL and CMOS characteristics Week 4 Lab 2: Astable multivibrators (74123 &555) & Schmitt triggers, Week 5 Lab 3: Monostable multivibrators (74123 & 555) & power-on reset Week 6 Lab 4: Decoder applications Week 7 Holiday Week 8 Introduction to VHDL Week 9 Lab 5: Combinational Circuit Design Using FPGA I Week 10 Lab 5: Combinational Circuit Design Using FPGA II Week 11 Lab 6: Frequency counters I Week 12 Lab 6: Frequency counters II Week 13 Lab 7: Serial communications Week 14 Lab 7: Serial communications Week 15 Lab 8: Sequential circuit design using FPGA I Week 16 Lab 8: Sequential circuit design using FPGA II Week 17 Final exam

評量方式與標準 Participation and check off worked circuits: 60% Lab reports: 20 % Final exam: 20 % (*) * The final exam covers basic knowledge students should know to successfully complete the lab experiments. Students whose final exam scores below 33 points are determined not to have enough knowledge to complete the experiments independently. Therefore, the instructor reserve the rights not to count the points of some worked circuits and reports for those students.

使用教材、參考書目或其他 【遵守智慧財產權觀念，請使用正版教科書，不得使用非法影印教科書】

使用外文原文書：否
Lecture notes and reference datasheets are available as handouts.

課程諮詢管道我的研究室: 科研大樓1533
我的email：scyou@ntut.edu.tw。

課程對應SDGs指標

備註
若學校因應疫情規定遠距教學，則使用Microsoft Teams平台上課
1. 學校的 Microsoft Teams 使用（學號@cc.ntut.edu.tw）登入
2. 我的email：scyou@ntut.edu.tw。

4/19 停課,安排2/27, 3/5, 與 3/26 10:10 - 11:00 補課

教師姓名	尤信程　教師諮商時間(Office Hours)
Email	scyou@ntut.edu.tw
最後更新時間	2024-03-11 10:47:51
課程大綱	１.TTL，CMOS邏輯閘之特性實習２.組合邏輯電路設計實習含：算術電路，比較器，解碼器，編碼器，多工器，解多工器等３.序向邏輯電路設計與應用：正反器，計數器，記錄器，及移位暫存器等綜合應用４.FPGA設計規劃。
課程進度	Week 1 General announcement and lab administration Week 2 Lab 0: Use of lab equipment Week 3 Lab 1: TTL and CMOS characteristics Week 4 Lab 2: Astable multivibrators (74123 &555) & Schmitt triggers, Week 5 Lab 3: Monostable multivibrators (74123 & 555) & power-on reset Week 6 Lab 4: Decoder applications Week 7 Holiday Week 8 Introduction to VHDL Week 9 Lab 5: Combinational Circuit Design Using FPGA I Week 10 Lab 5: Combinational Circuit Design Using FPGA II Week 11 Lab 6: Frequency counters I Week 12 Lab 6: Frequency counters II Week 13 Lab 7: Serial communications Week 14 Lab 7: Serial communications Week 15 Lab 8: Sequential circuit design using FPGA I Week 16 Lab 8: Sequential circuit design using FPGA II Week 17 Final exam
評量方式與標準	Participation and check off worked circuits: 60% Lab reports: 20 % Final exam: 20 % () The final exam covers basic knowledge students should know to successfully complete the lab experiments. Students whose final exam scores below 33 points are determined not to have enough knowledge to complete the experiments independently. Therefore, the instructor reserve the rights not to count the points of some worked circuits and reports for those students.
使用教材、參考書目或其他	【遵守智慧財產權觀念，請使用正版教科書，不得使用非法影印教科書】使用外文原文書：否 Lecture notes and reference datasheets are available as handouts.
課程諮詢管道	我的研究室: 科研大樓1533 我的email：scyou@ntut.edu.tw。
課程對應SDGs指標
備註	若學校因應疫情規定遠距教學，則使用Microsoft Teams平台上課 1. 學校的 Microsoft Teams 使用（學號@cc.ntut.edu.tw）登入 2. 我的email：scyou@ntut.edu.tw。 4/19 停課,安排2/27, 3/5, 與 3/26 10:10 - 11:00 補課