Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Spring Semester
Year 2024 328269 Mixed-Signal Integrated Circuit Design 1 3.0 3 ★ CHIU HUNG WEI ECE
IEECSG 44 0 電子所與電資外生所合開

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Spring Semester Year 2024	328269	Mixed-Signal Integrated Circuit Design	1	3.0	3	★	CHIU HUNG WEI	ECE IEECSG	44	0	電子所與電資外生所合開

Course Plan：

Instructor CHIU HUNG WEI　Office Hours

Email hwchiu@ntut.edu.tw

Last Updated 2023-12-12 08:43:01

Course Objective This course offers an in-depth exploration into the analysis and design of mixed-signal integrated circuits (ICs), with a particular emphasis on signal conversion and system modeling. The curriculum is structured around four main pillars (MLDS) : (1) Modeling - the development of mixed-signal circuits, (2) Language - proficiency in programming languages such as Verilog-A, Verilog-D, Python, C, and Matlab, (3) Data/Signal - thorough analysis of circuit performance and signal quality, and (4) System - mastery in adaptive optimization algorithms. Practical examples, including voltage regulators, Phase-Locked Loops (PLLs), and Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs), will be used to reinforce learning.

Course Schedule Week 1-3: Fundamentals of Closed-Loop Systems Week 4-5: MATLAB Modeling of PLL Week 6-7: Verilog-A Modeling of PLL Week 8-9: Verilog-D Simulation of PLL Week 10: Circuit Synthesis Week 11-12: Mixed-Signal Simulation Techniques Week 13: Mid-Term Project Assignment Week 14-15: Theoretical Concepts of SAR ADC Week 16-17: Analysis and Design of SAR ADC Week 18: Final Project Submission

Evaluation and grading policy Prerequisites: 1. Fundamental Microelectronics 2. Basic VLSI Design 3. Familiarity with Computing Languages (MATLAB, Verilog, Python) Grading Distribution: • Homework Assignments: 30% • Attendance and In-Class Exercises: 10% • Mid-Term Project: 30% • Final Project: 30%

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:No
References: 1. "CMOS Analog Circuit Design" by Allen 2. "CMOS Mixed-Signal Circuit Design" by R. Jacob Baker 2022 Assignment and Project Examples: • MSD-HW1: Simulation of feedback amplifier's transient response with specific initial conditions using programming languages. Submission of code and output files within two weeks. • MSD-HW2: Numerical transient analysis of a nonlinear feedback amplifier using mathematical tools. Submission includes code files. • MSD-HW3: Calculation of resistance in a mesh network using linear algebra, verified with Hspice, to be submitted within one month. • MSD-HW4: Generation and spectral analysis of a 10-Hz sinusoidal wave using MATLAB, Mathematica, or Python. Submission of solutions and spectrum graph within one month. • MSD-HW5: PLL linear model design and system stability verification using MATLAB and other tools. Submission of various files and screenshots within one month. • MSD-HW6: Design and simulation of an integer divider for PLL in Verilog, verified through digital design flow. Submission of code and waveform screenshots within one month. • Final Report - PLL Locking Simulation: Design of an integer PLL with a report including design flow, simulations, and Verilog files. Submission of comprehensive files by the deadline.

The access to curricular consultation Course Line and Teams group.

The course corresponds to the SDGs

Note
SDG12

Instructor	CHIU HUNG WEI　Office Hours
Email	hwchiu@ntut.edu.tw
Last Updated	2023-12-12 08:43:01
Course Objective	This course offers an in-depth exploration into the analysis and design of mixed-signal integrated circuits (ICs), with a particular emphasis on signal conversion and system modeling. The curriculum is structured around four main pillars (MLDS) : (1) Modeling - the development of mixed-signal circuits, (2) Language - proficiency in programming languages such as Verilog-A, Verilog-D, Python, C, and Matlab, (3) Data/Signal - thorough analysis of circuit performance and signal quality, and (4) System - mastery in adaptive optimization algorithms. Practical examples, including voltage regulators, Phase-Locked Loops (PLLs), and Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs), will be used to reinforce learning.
Course Schedule	Week 1-3: Fundamentals of Closed-Loop Systems Week 4-5: MATLAB Modeling of PLL Week 6-7: Verilog-A Modeling of PLL Week 8-9: Verilog-D Simulation of PLL Week 10: Circuit Synthesis Week 11-12: Mixed-Signal Simulation Techniques Week 13: Mid-Term Project Assignment Week 14-15: Theoretical Concepts of SAR ADC Week 16-17: Analysis and Design of SAR ADC Week 18: Final Project Submission
Evaluation and grading policy	Prerequisites: 1. Fundamental Microelectronics 2. Basic VLSI Design 3. Familiarity with Computing Languages (MATLAB, Verilog, Python) Grading Distribution: • Homework Assignments: 30% • Attendance and In-Class Exercises: 10% • Mid-Term Project: 30% • Final Project: 30%
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:No References: 1. "CMOS Analog Circuit Design" by Allen 2. "CMOS Mixed-Signal Circuit Design" by R. Jacob Baker 2022 Assignment and Project Examples: • MSD-HW1: Simulation of feedback amplifier's transient response with specific initial conditions using programming languages. Submission of code and output files within two weeks. • MSD-HW2: Numerical transient analysis of a nonlinear feedback amplifier using mathematical tools. Submission includes code files. • MSD-HW3: Calculation of resistance in a mesh network using linear algebra, verified with Hspice, to be submitted within one month. • MSD-HW4: Generation and spectral analysis of a 10-Hz sinusoidal wave using MATLAB, Mathematica, or Python. Submission of solutions and spectrum graph within one month. • MSD-HW5: PLL linear model design and system stability verification using MATLAB and other tools. Submission of various files and screenshots within one month. • MSD-HW6: Design and simulation of an integer divider for PLL in Verilog, verified through digital design flow. Submission of code and waveform screenshots within one month. • Final Report - PLL Locking Simulation: Design of an integer PLL with a report including design flow, simulations, and Verilog files. Submission of comprehensive files by the deadline.
The access to curricular consultation	Course Line and Teams group.
The course corresponds to the SDGs
Note	SDG12