Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Spring Semester
Year 2021 288141 Advanced FPGA Design 1 3.0 3 ★ Kuan-Ting Lai 4EN4A
4EN4B 18 0 綜科501，電子四甲乙合開

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Spring Semester Year 2021	288141	Advanced FPGA Design	1	3.0	3	★	Kuan-Ting Lai	4EN4A 4EN4B	18	0	綜科501，電子四甲乙合開

Course Plan：

Instructor Kuan-Ting Lai

Email ktlai@ntut.edu.tw

Last Updated 2020-12-22 00:30:53

Course Objective 本課程將以Xilinx PYNQ Z2為平台, 教授學生FPGA程式開發、硬體系統設計、和如何利用FPGA加速深度學習演算法。主要內容包括Xilinx Vivado和Vitis開發環境, High-level Synthesis (HLS) & SystemC, 基本FIR filter和矩陣乘法的設計, 以及類神經網路的模型移植等等。

Course Schedule 1. Xilinx & Vivado IDE 2. High-level Synthesis (HLS) & SystemC 3. Finite Impulse Response (FIR) Filters 4. Discrete Fourier Transform & Fast Fourier Transform 5. Matrix Multiplication 6. Prefix Sum and Histogram 7. Video Systems 8. Deep Learning Implementation on FPGA 9. Pruning & Quantization 10. Object Detection on FPGA This course teaches FPGA programming, hardware system design, and how to implement and accelerate Deep Learning Algorithms on FPGA. The syllabus is shown below: 1. Xilinx & Vivado IDE 2. High-level Synthesis (HLS) & SystemC 3. Finite Impulse Response (FIR) Filters 4. Discrete Fourier Transform & Fast Fourier Transform 5. Matrix Multiplication 6. Prefix Sum and Histogram 7. Video Systems 8. Deep Learning Implementation on FPGA 9. Pruning & Quantization 10. Object Detection on FPGA

Evaluation and grading policy Labs (70%), Final Project (30%)

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:Yes
KRG @ UC San Diego, “Parallel Programming for FPGAs”, 2018 自製講義

The access to curricular consultation

Note
　

Instructor	Kuan-Ting Lai
Email	ktlai@ntut.edu.tw
Last Updated	2020-12-22 00:30:53
Course Objective	本課程將以Xilinx PYNQ Z2為平台, 教授學生FPGA程式開發、硬體系統設計、和如何利用FPGA加速深度學習演算法。主要內容包括Xilinx Vivado和Vitis開發環境, High-level Synthesis (HLS) & SystemC, 基本FIR filter和矩陣乘法的設計, 以及類神經網路的模型移植等等。
Course Schedule	1. Xilinx & Vivado IDE 2. High-level Synthesis (HLS) & SystemC 3. Finite Impulse Response (FIR) Filters 4. Discrete Fourier Transform & Fast Fourier Transform 5. Matrix Multiplication 6. Prefix Sum and Histogram 7. Video Systems 8. Deep Learning Implementation on FPGA 9. Pruning & Quantization 10. Object Detection on FPGA This course teaches FPGA programming, hardware system design, and how to implement and accelerate Deep Learning Algorithms on FPGA. The syllabus is shown below: 1. Xilinx & Vivado IDE 2. High-level Synthesis (HLS) & SystemC 3. Finite Impulse Response (FIR) Filters 4. Discrete Fourier Transform & Fast Fourier Transform 5. Matrix Multiplication 6. Prefix Sum and Histogram 7. Video Systems 8. Deep Learning Implementation on FPGA 9. Pruning & Quantization 10. Object Detection on FPGA
Evaluation and grading policy	Labs (70%), Final Project (30%)
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:Yes KRG @ UC San Diego, “Parallel Programming for FPGAs”, 2018 自製講義
The access to curricular consultation
Note