Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Spring Semester
Year 2021 287302 Digital System Design 1 3.0 3 ★ Yun-Chao Chen 4EN3C 17 1 綜科501，日職合開

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Spring Semester Year 2021	287302	Digital System Design	1	3.0	3	★	Yun-Chao Chen	4EN3C	17	1	綜科501，日職合開

Course Plan：

Instructor Yun-Chao Chen

Email mikechen@ieee.org

Last Updated 2021-02-03 09:55:06

Course Objective 由於 VHDL 和 Verilog 都廣泛用於數位系統設計中，因此將兩種設計組合在一起而不是將 Verilog 代碼轉換為 VHDL，或者是將 VHDL 代碼轉換為 Verilog，將更能有益於數位系統的設計。本課程介紹 Verilog 與 VHDL 的單獨設計及混合軟體的設計與使用。使用ModelSim, Quartus II 等軟體及 FPGA 來證實，並使用 AD2 的 Digital Pattern Generator 和L ogic Analyzer來做硬體測試的示範。

Course Schedule 1. 2/25 : Introduction to Digital System Design 2. 3/4: Design case with HDL Verilog and VHDL 3. 3/11: Data types with Verilog ad VHDL 4. 3/18: Concurrent codes in Verilog and VHDL 5. 3/25: Quiz 1 6. 4/1: Sequential codes in Verilog and VHDL 7. 4/8: Procedural assignment in Verilog and VHDL 8. 4/15: TestBench for Verilog and VHDL testing 9. 4/22: 期中考試 10. 4/29: Introduction to ModelSim Simulator 11. 5/6: Modeling styles in Verilog and VHDL 12. 5/13: FSM in Verilog and VHDL 13. 5/20: Quiz 2 14. 5/27: VHDL designs in Verilog 15. 6/3: Introduction to Quartus II Synthesis 16. 6/10: Introduction to FPGA testing AD2 17. 6/17: A complete Digital Design Example with FPGA 18. 6/24: 期末考試

Evaluation and grading policy Homework 20% Quiz 2 次 20% Mid term test 30% Final test 30%

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:Yes
HDL Programming Fundamentals VHDL and Verilog 2006 / Nazeib M. Botros Circuit Design and Simulation with VHDL, second edition 2010 / Volnei A. Pedroni Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition 2003 / Samir Palnitkar iLAB-FPGA / 2016 陳雲潮講義 (powerpoint and files 同學在上課前可上網下載)

The access to curricular consultation

Note
　

Instructor	Yun-Chao Chen
Email	mikechen@ieee.org
Last Updated	2021-02-03 09:55:06
Course Objective	由於 VHDL 和 Verilog 都廣泛用於數位系統設計中，因此將兩種設計組合在一起而不是將 Verilog 代碼轉換為 VHDL，或者是將 VHDL 代碼轉換為 Verilog，將更能有益於數位系統的設計。本課程介紹 Verilog 與 VHDL 的單獨設計及混合軟體的設計與使用。使用ModelSim, Quartus II 等軟體及 FPGA 來證實，並使用 AD2 的 Digital Pattern Generator 和L ogic Analyzer來做硬體測試的示範。
Course Schedule	1. 2/25 : Introduction to Digital System Design 2. 3/4: Design case with HDL Verilog and VHDL 3. 3/11: Data types with Verilog ad VHDL 4. 3/18: Concurrent codes in Verilog and VHDL 5. 3/25: Quiz 1 6. 4/1: Sequential codes in Verilog and VHDL 7. 4/8: Procedural assignment in Verilog and VHDL 8. 4/15: TestBench for Verilog and VHDL testing 9. 4/22: 期中考試 10. 4/29: Introduction to ModelSim Simulator 11. 5/6: Modeling styles in Verilog and VHDL 12. 5/13: FSM in Verilog and VHDL 13. 5/20: Quiz 2 14. 5/27: VHDL designs in Verilog 15. 6/3: Introduction to Quartus II Synthesis 16. 6/10: Introduction to FPGA testing AD2 17. 6/17: A complete Digital Design Example with FPGA 18. 6/24: 期末考試
Evaluation and grading policy	Homework 20% Quiz 2 次 20% Mid term test 30% Final test 30%
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:Yes HDL Programming Fundamentals VHDL and Verilog 2006 / Nazeib M. Botros Circuit Design and Simulation with VHDL, second edition 2010 / Volnei A. Pedroni Verilog HDL: A Guide to Digital Design and Synthesis, Second Edition 2003 / Samir Palnitkar iLAB-FPGA / 2016 陳雲潮講義 (powerpoint and files 同學在上課前可上網下載)
The access to curricular consultation
Note