Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Spring Semester
Year 2021 285861 VLSI Design 1 3.0 3 ★ De-Yu Kao 攜四子四
訓四子四 16 5 訓四子四與攜四子四合開

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Spring Semester Year 2021	285861	VLSI Design	1	3.0	3	★	De-Yu Kao	攜四子四訓四子四	16	5	訓四子四與攜四子四合開

Course Plan：

Instructor De-Yu Kao

Email kao_deyu@yahoo.com

Last Updated 2020-12-09 10:15:14

Course Objective *Memories -Sequential Machines -Memory devices: Latch & FF -RAM & ROM -DFT, MEM BIST -State assignment *Packaging *ALU design -Adders -Multiplier *Backend Design -APR -Special Net -Misc. *Architecture *Examples

Course Schedule week / date / topics 01. 02/26/21 Chapter 5 (Memory types, Set-up & hold time) 02. 03/05/21 Chapter 5 (Memory devices: Latch, FF, & ROM) 03. 03/12/21 Chapter 5 (Memory devices: RAM , Clock skew) 04. 03/19/21 Chapter 5 (Memory timing and clock, Testing) 05. 03/26/21 (QZ1)Chapter 5 (Sequential machine, State graph) 06. 04/02/21 兒童節 07. 04/09/21 Packaging (Packaging flow) 08. 04/16/21 Midterm Examination 09. 04/23/21 Exam review , Packaging (Relibility) 10. 04/30/21 Chapter 6 (ALU, adder) 11. 05/07/21 Chapter 6 (Multiplier) 12. 05/14/21 Chapter 7 (Placement) 13. 05/21/21 Chapter 7 (Routing, Special nets) 14. 05/28/21 Chapter 8 (Architecture) 15. 06/04/21 (QZ2) Chapter 8 (Architecture) 16. 06/11/21 Chapter 9 (Example) 17. 06/18/21 Final Examination 18. 06/25/21 Exam review, What’s Next?

Evaluation and grading policy Two quizzes 30% (15% for each) Midterm 35% Final 35%

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:Yes
Textbook: Modern VLSI Design System-on-Chip Design, Prentice Hall, by: Wayne Wolf References: ULSI 製程技術 (新文京開發出版) by: 劉博文 Digital Integrated Circuits A Design Perspective By: Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Class Notes online: https://myweb.ntut.edu.tw/~dkao/

The access to curricular consultation

Note
　

Instructor	De-Yu Kao
Email	kao_deyu@yahoo.com
Last Updated	2020-12-09 10:15:14
Course Objective	Memories -Sequential Machines -Memory devices: Latch & FF -RAM & ROM -DFT, MEM BIST -State assignment Packaging ALU design -Adders -Multiplier Backend Design -APR -Special Net -Misc. Architecture Examples
Course Schedule	week / date / topics 01. 02/26/21 Chapter 5 (Memory types, Set-up & hold time) 02. 03/05/21 Chapter 5 (Memory devices: Latch, FF, & ROM) 03. 03/12/21 Chapter 5 (Memory devices: RAM , Clock skew) 04. 03/19/21 Chapter 5 (Memory timing and clock, Testing) 05. 03/26/21 (QZ1)Chapter 5 (Sequential machine, State graph) 06. 04/02/21 兒童節 07. 04/09/21 Packaging (Packaging flow) 08. 04/16/21 Midterm Examination 09. 04/23/21 Exam review , Packaging (Relibility) 10. 04/30/21 Chapter 6 (ALU, adder) 11. 05/07/21 Chapter 6 (Multiplier) 12. 05/14/21 Chapter 7 (Placement) 13. 05/21/21 Chapter 7 (Routing, Special nets) 14. 05/28/21 Chapter 8 (Architecture) 15. 06/04/21 (QZ2) Chapter 8 (Architecture) 16. 06/11/21 Chapter 9 (Example) 17. 06/18/21 Final Examination 18. 06/25/21 Exam review, What’s Next?
Evaluation and grading policy	Two quizzes 30% (15% for each) Midterm 35% Final 35%
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:Yes Textbook: Modern VLSI Design System-on-Chip Design, Prentice Hall, by: Wayne Wolf References: ULSI 製程技術 (新文京開發出版) by: 劉博文 Digital Integrated Circuits A Design Perspective By: Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Class Notes online: https://myweb.ntut.edu.tw/~dkao/
The access to curricular consultation
Note