Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Spring Semester
Year 2021 282781 Digital System Design Lab. 1 1.0 3 ▲ CHUNG-PING CHEN 4EN3A
4EN3B 58 0 綜科501，電子三甲乙合開

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Spring Semester Year 2021	282781	Digital System Design Lab.	1	1.0	3	▲	CHUNG-PING CHEN	4EN3A 4EN3B	58	0	綜科501，電子三甲乙合開

Course Plan：

Instructor CHUNG-PING CHEN

Email cpchen@ntut.edu.tw

Last Updated 2020-12-07 11:58:42

Course Objective 本課程內容包括邏輯閘的特性與功能測試，能利用積體電路完成各種基礎邏輯電路的組裝及設計，並能利用電子儀器進行量測、檢修。探討最佳化組合邏輯之演算法，可規劃邏輯元件，組合邏輯之VLSI設計，使用MSI與標準電路元件設計多層邏輯，使用閘陣列設計，循序邏輯之元件，循序邏輯之分析與合成，VLSI之設計與測試技巧，各種CAD軟體工具介紹。基礎邏輯閘實驗、組合邏輯實驗、加法器及減法器實驗、組合邏輯應用實驗、正反器邏輯實驗、循序邏輯電路應用實驗。

Course Schedule Week- 1 Introduction to Digital System Design Week- 2 Concurrent Code and Devices Design Week- 3 Simulation with VHDL Testbench Week- 4 Testing with Pattern Generator and Digital Analyzer Week- 5 Sequential Code and Devices Design Week- 6 Sequential Code and Devices Design Week- 7 Signal and Variables Week- 8 考前複習 Week- 9 Midterm test Week- 10 Package and Component for System design Week- 11 Function and Procedure in System Design Week- 12 Design with State Machines Week- 13 Introduction to DE2-115 Week- 14 Memoy and NIOS soft CPU and FPGA Week- 15 Synthesis with Quartus II Week- 16 Qsys and NIOS-SOC Week- 17 Final Test Week- 18 補考

Evaluation and grading policy 1. Two Quizes 20% 2. Mid term test 20% 3. Final test 20% 4. Home works 40%

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:Yes
1. Text Book: Circuit Design and Simulation with VHDL 2nd Edition Volnei A.pedroni / The MIT Press 2010 2. Reference Book: Finite State Machine in Hardware Volnei A.pedroni / The MIT Press 2013 3. Reference Book: Digital System Design with VHDL 2nd Edition Mark Zwolinski / Pearson 2004 4. Lab Book: iLAB-FPGA 數位系統設計摸擬測試與硬體除錯陳雲潮 / 東華書局 2016

The access to curricular consultation

Note
　

Instructor	CHUNG-PING CHEN
Email	cpchen@ntut.edu.tw
Last Updated	2020-12-07 11:58:42
Course Objective	本課程內容包括邏輯閘的特性與功能測試，能利用積體電路完成各種基礎邏輯電路的組裝及設計，並能利用電子儀器進行量測、檢修。探討最佳化組合邏輯之演算法，可規劃邏輯元件，組合邏輯之VLSI設計，使用MSI與標準電路元件設計多層邏輯，使用閘陣列設計，循序邏輯之元件，循序邏輯之分析與合成，VLSI之設計與測試技巧，各種CAD軟體工具介紹。基礎邏輯閘實驗、組合邏輯實驗、加法器及減法器實驗、組合邏輯應用實驗、正反器邏輯實驗、循序邏輯電路應用實驗。
Course Schedule	Week- 1 Introduction to Digital System Design Week- 2 Concurrent Code and Devices Design Week- 3 Simulation with VHDL Testbench Week- 4 Testing with Pattern Generator and Digital Analyzer Week- 5 Sequential Code and Devices Design Week- 6 Sequential Code and Devices Design Week- 7 Signal and Variables Week- 8 考前複習 Week- 9 Midterm test Week- 10 Package and Component for System design Week- 11 Function and Procedure in System Design Week- 12 Design with State Machines Week- 13 Introduction to DE2-115 Week- 14 Memoy and NIOS soft CPU and FPGA Week- 15 Synthesis with Quartus II Week- 16 Qsys and NIOS-SOC Week- 17 Final Test Week- 18 補考
Evaluation and grading policy	1. Two Quizes 20% 2. Mid term test 20% 3. Final test 20% 4. Home works 40%
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:Yes 1. Text Book: Circuit Design and Simulation with VHDL 2nd Edition Volnei A.pedroni / The MIT Press 2010 2. Reference Book: Finite State Machine in Hardware Volnei A.pedroni / The MIT Press 2013 3. Reference Book: Digital System Design with VHDL 2nd Edition Mark Zwolinski / Pearson 2004 4. Lab Book: iLAB-FPGA 數位系統設計摸擬測試與硬體除錯陳雲潮 / 東華書局 2016
The access to curricular consultation
Note