Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Spring Semester
Year 2025 345589 FPGA System Design Practice 1 3.0 3 ★ TRONG-YEN LEE 4EN3A
4EN3B 40 3 電子大三合開

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Spring Semester Year 2025	345589	FPGA System Design Practice	1	3.0	3	★	TRONG-YEN LEE	4EN3A 4EN3B	40	3	電子大三合開

Course Plan：

Instructor TRONG-YEN LEE

Email tylee@ntut.edu.tw

Last Updated 2024-12-18 08:49:12

Course Objective (1)簡介 (2)FPGA系統 (3)FPGA結構 (4)組合邏輯設計 (5)順序機設計 (6)FPGA雛形系統設計 (7)FPGA雛形系統驗證 (8)大型系統設計 (1)Introduction (2)FPGA-Based Systems (3)FPGA Fabrics (4)Combinational Logic Design (5)Sequential Machines Design (6)FPGA Prototyping Systems Design (7)FPGA Prototyping Systems Verification (8)Large-Scale Systems Design

Course Schedule 第一週--Chapter 1. Introduction 第二週--Chapter 2. Digital Logic Design Using Hardware Description Languages; Lab 1 - Digital Circuits Design By Xilinx ISE 第三週--Chapter 2. Digital Logic Design Using Hardware Dscription Languages; Lab 2 - Module-Based Digital Circuit Design and Verification 第四週--Chapter 3. Introduction to Verilog and Test Benches 第五週--Chapter 4. High-Level Verilog Coding for Synthesis Lab 3 - Tutorial using HDL Based Design 第六週--Chapter 4. High-Level Verilog Coding for Synthesis 第七週--Chapter 5. State Machine Design 第八週--Chapter 5. State Machine Design Lab 4 - Design a 4-bit up-down Counter 第九週--期中考第十週--Chapter 6. FPGA and Other Programmable Logic Devices 第十一週--Chapter 6. FPGA and Other Programmable Logic Devices Lab 5 - Design and Implementation 第十二週--Chapter 7. Design of a USB Protocol Analyzer 第十三週--Chapter 7. Design of a USB Protocol Analyzer 第十四週--Chapter 8. Design of Fast Arithmetic Units 第十五週--Chapter 8. Design of Fast Arithmetic Units 第十六週--Chapter 9. Design of a Pipelined RISC Microprocessor (Option): 第十七週--期末考筆試第十八週--上機實作考試

Evaluation and grading policy 1.平時成績(含平常考、實驗、作業、出席及表現、上機實作考試) 40% 2.期中考30% 3.期末考30%

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:Yes
Text Book: Advanced Digital Logic Design Using Verilog, State Machines, and Synthesis for FPGAs Reference book or papers 1. Rapid System Prototyping with FPGAs by R.C.Cofer and Ben Harding, Newnes, 2006. 2. Wayne Wolf, FPGA-Based System Design, Prentice Hall, 2004. hppt://www.xilinx.com/support/support.htm

The access to curricular consultation 老師的信箱: tylee@ntut.edu.tw

The course corresponds to the SDGs 無（None）

Does the course incorporate AI

Note
(1)若採用遠距教學，上課方式將使用Google Meet視訊軟體進行，連結為https://meet.google.com/hrb-cqap-iuv
(2)上課教材投影片: 上課時公布。

Instructor	TRONG-YEN LEE
Email	tylee@ntut.edu.tw
Last Updated	2024-12-18 08:49:12
Course Objective	(1)簡介 (2)FPGA系統 (3)FPGA結構 (4)組合邏輯設計 (5)順序機設計 (6)FPGA雛形系統設計 (7)FPGA雛形系統驗證 (8)大型系統設計 (1)Introduction (2)FPGA-Based Systems (3)FPGA Fabrics (4)Combinational Logic Design (5)Sequential Machines Design (6)FPGA Prototyping Systems Design (7)FPGA Prototyping Systems Verification (8)Large-Scale Systems Design
Course Schedule	第一週--Chapter 1. Introduction 第二週--Chapter 2. Digital Logic Design Using Hardware Description Languages; Lab 1 - Digital Circuits Design By Xilinx ISE 第三週--Chapter 2. Digital Logic Design Using Hardware Dscription Languages; Lab 2 - Module-Based Digital Circuit Design and Verification 第四週--Chapter 3. Introduction to Verilog and Test Benches 第五週--Chapter 4. High-Level Verilog Coding for Synthesis Lab 3 - Tutorial using HDL Based Design 第六週--Chapter 4. High-Level Verilog Coding for Synthesis 第七週--Chapter 5. State Machine Design 第八週--Chapter 5. State Machine Design Lab 4 - Design a 4-bit up-down Counter 第九週--期中考第十週--Chapter 6. FPGA and Other Programmable Logic Devices 第十一週--Chapter 6. FPGA and Other Programmable Logic Devices Lab 5 - Design and Implementation 第十二週--Chapter 7. Design of a USB Protocol Analyzer 第十三週--Chapter 7. Design of a USB Protocol Analyzer 第十四週--Chapter 8. Design of Fast Arithmetic Units 第十五週--Chapter 8. Design of Fast Arithmetic Units 第十六週--Chapter 9. Design of a Pipelined RISC Microprocessor (Option): 第十七週--期末考筆試第十八週--上機實作考試
Evaluation and grading policy	1.平時成績(含平常考、實驗、作業、出席及表現、上機實作考試) 40% 2.期中考30% 3.期末考30%
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:Yes Text Book: Advanced Digital Logic Design Using Verilog, State Machines, and Synthesis for FPGAs Reference book or papers 1. Rapid System Prototyping with FPGAs by R.C.Cofer and Ben Harding, Newnes, 2006. 2. Wayne Wolf, FPGA-Based System Design, Prentice Hall, 2004. hppt://www.xilinx.com/support/support.htm
The access to curricular consultation	老師的信箱: tylee@ntut.edu.tw
The course corresponds to the SDGs	無（None）
Does the course incorporate AI
Note	(1)若採用遠距教學，上課方式將使用Google Meet視訊軟體進行，連結為https://meet.google.com/hrb-cqap-iuv (2)上課教材投影片: 上課時公布。