Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Spring Semester
Year 2023 317127 Digital System Design 1 3.0 3 ★ Kuo,Hung-Yuan 訓四子三 51 0 　

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Spring Semester Year 2023	317127	Digital System Design	1	3.0	3	★	Kuo,Hung-Yuan	訓四子三	51	0

Course Plan：

Instructor Kuo,Hung-Yuan　Office Hours

Email hungyuankuo@ntut.edu.tw

Last Updated 2022-12-13 09:42:31

Course Objective 最佳化組合邏輯與循序邏輯之演算法，可規劃邏輯元件，組合邏輯之VLSI設計，使用MSI與標準電路元件設計多層邏輯，使用閘陣列設計，循序邏輯之元件，循序邏輯之分析與合成，StateMachine設計與測試技巧，HDL語法介紹與實務設計。

Course Schedule 1. Review of Logic Design Fundamentals 2. Combinational Logic 3. CMOS Digital Logic Circuits 4. Mealy/Moore Sequential Circuit Design 5. Equivalent States and Reduction of State Tables 6. Sequential Circuit Timing 7. Programmable Logic Devices(PLD) 8. Field-Programmable Gate Arrays (FPGAs) 9. Midterm Exam. 10. Hardware Description Languages 11. VHDL & Verilog Modules 12. Digital Circuit Example 13. Serial Communication 14. Arithmetic Logic Unit Design 15. Floating-Point Arithmetic 16. RISC Microprocessor 17. MIPS Instruction Encoding 18. Final Exam.

Evaluation and grading policy 平時: 30% 期中考: 35% 期末考: 35%

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:Yes
1. "Digital Systems Design Using VHDL", Charles H. Roth & Lizy K. John, 2018, ISBN：9781305638921, Cengage 2. "Digital Systems: Principles and Applications", Tocci, 2011/11, ISBN-13：9780130387936, Pearson Education 3. "Fundamentals of Digital Logic with VHDL Design", Stephen Brown, 2009/3, ISBN：9780071287654, Mc Graw Hill

The access to curricular consultation 研究室：綜科館 209-3 室
E-mail : hungyuankuo@mail.ntut.edu.tw

The course corresponds to the SDGs

Note
上課教材 : 北科i學園+ (校園入口網站 => 教務系統 => 北科i學園PLUS => 我的課程 => 學習互動區 => 教材及錄影
上課作業 : 北科i學園+ (校園入口網站 => 教務系統 => 北科i學園PLUS => 我的課程 => 評量區 => 作業/報告

Instructor	Kuo,Hung-Yuan　Office Hours
Email	hungyuankuo@ntut.edu.tw
Last Updated	2022-12-13 09:42:31
Course Objective	最佳化組合邏輯與循序邏輯之演算法，可規劃邏輯元件，組合邏輯之VLSI設計，使用MSI與標準電路元件設計多層邏輯，使用閘陣列設計，循序邏輯之元件，循序邏輯之分析與合成，StateMachine設計與測試技巧，HDL語法介紹與實務設計。
Course Schedule	1. Review of Logic Design Fundamentals 2. Combinational Logic 3. CMOS Digital Logic Circuits 4. Mealy/Moore Sequential Circuit Design 5. Equivalent States and Reduction of State Tables 6. Sequential Circuit Timing 7. Programmable Logic Devices(PLD) 8. Field-Programmable Gate Arrays (FPGAs) 9. Midterm Exam. 10. Hardware Description Languages 11. VHDL & Verilog Modules 12. Digital Circuit Example 13. Serial Communication 14. Arithmetic Logic Unit Design 15. Floating-Point Arithmetic 16. RISC Microprocessor 17. MIPS Instruction Encoding 18. Final Exam.
Evaluation and grading policy	平時: 30% 期中考: 35% 期末考: 35%
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:Yes 1. "Digital Systems Design Using VHDL", Charles H. Roth & Lizy K. John, 2018, ISBN：9781305638921, Cengage 2. "Digital Systems: Principles and Applications", Tocci, 2011/11, ISBN-13：9780130387936, Pearson Education 3. "Fundamentals of Digital Logic with VHDL Design", Stephen Brown, 2009/3, ISBN：9780071287654, Mc Graw Hill
The access to curricular consultation	研究室：綜科館 209-3 室 E-mail : hungyuankuo@mail.ntut.edu.tw
The course corresponds to the SDGs
Note	上課教材 : 北科i學園+ (校園入口網站 => 教務系統 => 北科i學園PLUS => 我的課程 => 學習互動區 => 教材及錄影上課作業 : 北科i學園+ (校園入口網站 => 教務系統 => 北科i學園PLUS => 我的課程 => 評量區 => 作業/報告