Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Fall Semester
Year 2025 347550 Digital System 1 3.0 3 ★ Jun-Lin Liu 4EE3C 50 0 預選限50人。

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Fall Semester Year 2025	347550	Digital System	1	3.0	3	★	Jun-Lin Liu	4EE3C	50	0	預選限50人。

Course Plan：

Instructor Jun-Lin Liu　Office Hours

Email junlin@mail.ntut.edu.tw

Last Updated 2025-08-15 16:06:43

Course Objective 最佳化組合邏輯之演算法，可規劃邏輯元件，組合邏輯之VLSI設計，使用MSI與標準電路元件設計多層邏輯，使用閘陣列設計，循序邏輯之元件，循序邏輯之分析與合成，VLSI之設計與測試技巧，各種CALD軟體工具介紹。 1.Algorithms for Optimization of combinational logic 2.VLSI realizations of combination logic 3.Multilevel logic using complex parts and cells. 4.Components of sequential systems 5.Synthesis of clock-mode sequential circuits.

Course Schedule Week1: Review of Logic Design Fundamentals (1/3) Week2: Review of Logic Design Fundamentals (2/3) Week3: Review of Logic Design Fundamentals (3/3) Week4: Introduction to Verilog (1/3) Week5: Introduction to Verilog (2/3) Week6: Introduction to Verilog (3/3) Week7: Verilog Simulation and Testbench (1/2) Week8: Verilog Simulation and Testbench (2/2) Week9: Midterm Examination week10: Introduction to PLD Week11: Design Examples (1/2) Week12: Design Examples (2/2) Week13: Design Examples (3/3) Week14: SM Charts and Microprogramming (1/2) Week15: SM Charts and Microprogramming (2/2) Week16: Designing with FPGA (1/2) Week17: Designing with FPGA (2/2) Week18: Final Examination

Evaluation and grading policy Attendance: 10% Assignments: 25% Midterm Exam.: 30% Final Exam.: 35%

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:Yes
Textbook: Charles Roth, Lizy Kurian John, and Byeong Kil Lee, Digital Systems Design Using Verilog, International Edition, 2016, Cengage Learning Reference books: Logic and Computer Design Fundamentals, Morris Mano, Charles R. Kime, Tom Martin, 2016, Pearson

The access to curricular consultation 1.Office hours: (三) . 13:00 ~ 14:00, (四) 13:00 ~ 15:00, (五) 15:00 ~ 16:00 @綜科館215

2. Please email junlin@mail.ntut.edu.tw first to reserve the time for curricular consultation.

Expanding teaching and resources

The course corresponds to the SDGs SDG9：產業創新與基礎設施（Industry, Innovation and Infrastructure）

Does the course incorporate AI ● 簡單介紹AI的基本概念（Briefly introduce the basic concept of AI）

Note
　

Instructor	Jun-Lin Liu　Office Hours
Email	junlin@mail.ntut.edu.tw
Last Updated	2025-08-15 16:06:43
Course Objective	最佳化組合邏輯之演算法，可規劃邏輯元件，組合邏輯之VLSI設計，使用MSI與標準電路元件設計多層邏輯，使用閘陣列設計，循序邏輯之元件，循序邏輯之分析與合成，VLSI之設計與測試技巧，各種CALD軟體工具介紹。 1.Algorithms for Optimization of combinational logic 2.VLSI realizations of combination logic 3.Multilevel logic using complex parts and cells. 4.Components of sequential systems 5.Synthesis of clock-mode sequential circuits.
Course Schedule	Week1: Review of Logic Design Fundamentals (1/3) Week2: Review of Logic Design Fundamentals (2/3) Week3: Review of Logic Design Fundamentals (3/3) Week4: Introduction to Verilog (1/3) Week5: Introduction to Verilog (2/3) Week6: Introduction to Verilog (3/3) Week7: Verilog Simulation and Testbench (1/2) Week8: Verilog Simulation and Testbench (2/2) Week9: Midterm Examination week10: Introduction to PLD Week11: Design Examples (1/2) Week12: Design Examples (2/2) Week13: Design Examples (3/3) Week14: SM Charts and Microprogramming (1/2) Week15: SM Charts and Microprogramming (2/2) Week16: Designing with FPGA (1/2) Week17: Designing with FPGA (2/2) Week18: Final Examination
Evaluation and grading policy	Attendance: 10% Assignments: 25% Midterm Exam.: 30% Final Exam.: 35%
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:Yes Textbook: Charles Roth, Lizy Kurian John, and Byeong Kil Lee, Digital Systems Design Using Verilog, International Edition, 2016, Cengage Learning Reference books: Logic and Computer Design Fundamentals, Morris Mano, Charles R. Kime, Tom Martin, 2016, Pearson
The access to curricular consultation	1.Office hours: (三) . 13:00 ~ 14:00, (四) 13:00 ~ 15:00, (五) 15:00 ~ 16:00 @綜科館215 2. Please email junlin@mail.ntut.edu.tw first to reserve the time for curricular consultation.
Expanding teaching and resources
The course corresponds to the SDGs	SDG9：產業創新與基礎設施（Industry, Innovation and Infrastructure）
Does the course incorporate AI	● 簡單介紹AI的基本概念（Briefly introduce the basic concept of AI）
Note