Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Fall Semester
Year 2026 362806 Digital Logic Design 1 3.0 3 ▲ Hsiao-Chi Li 4EE1A 0 0 　

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Fall Semester Year 2026	362806	Digital Logic Design	1	3.0	3	▲	Hsiao-Chi Li	4EE1A	0	0

Course Plan：

Instructor Hsiao-Chi Li　Office Hours

Email hcli@mail.ntut.edu.tw

Last Updated 2026-06-11 09:03:57

Course Objective 本課程涵蓋以下主題： 1.數字的進制轉換以及二進制表示方式 2.布林代數式與函數 3.數位電路化簡技巧，如卡諾圖與製表法 4.組合邏輯電路，如：加法器/減法器、比較器、多工器、邊/解碼器 5.可編程邏輯電路，如：唯讀記憶體/可編程唯讀記憶體（ROM / PROM）、可編程邏輯電路（PLD）、可編程邏輯陣列（PLA） 6.順序邏輯電路，如：狀態機 Introduce the principles of digital logic. Topics includes: 1. Number representation, number bases and base conversions, and binary codes 2. Boolean algebra and functions 3. Combinational design techniques: K-maps, tabulation method 4. Combinational logic circuits: adders/subtractors, comparators, multiplexors/demultiplexers, and decoders/encoders 5. Programmable logic circuits: read-only memory/programmable read-only memory (ROM/PROM), programmable logic devices (PLD), and programmable logic arrays (PLA) 6. Sequential logic circuits: state machine

Course Schedule Week 1: Introduction Week 2-3: Boolean Algebra & Logic Gates Week 4: Minterm & Maxterm expansions Week 5-6: Karnaugh Maps Week 7-8: Quine-McClusky Method, Multi-Level Gate Circuits (1) Week 9: Midterm Exam Week 10: Multi-Level Gate Circuits (2) Week 11: Combinational Circuit Design and Simulation Using Gates Week 12-13: Multiplexers, Decoders, and Programmable Logic Devices Week 14-15: Latches and Flip-Flops Week 16: Registers and Counters, Analysis of Clocked Sequential Circuits Week 17: Derivation of State Graphs and Tables Week 18: Final Exam

Evaluation and grading policy Homework + Quiz 30% Midterm 30% Final 30% Attendance 10%

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:Yes
Charles H. Roth, Jr. and Larry L. Kinney, Fundamentals of Logic Design, Cengage, 7th Edition, 2013..

The access to curricular consultation Email: hcli@mail.ntut.edu.tw

Office hour: Tues & Weds 10:00 ~ 12:00 or by appointment

Expanding teaching and resources ● 數位科技融入 (Digital Technology Integration)
運用生成式AI、VR/AR、IoT、IRS等新興科技輔助教學與評量。
Utilizes emerging technologies such as Generative AI, VR/AR, IoT, and IRS (Interactive Response Systems) to facilitate teaching and assessment.

The course corresponds to the SDGs SDG4：優質教育（Quality Education）
SDG9：產業創新與基礎設施（Industry, Innovation and Infrastructure）

Does the course incorporate AI ● 使用生成式AI作為教學過程的輔助工具（Use generative AI tools as an aid to the teaching process）
● 鼓勵學生使用生成式AI工具（Encourage students to use generative AI tools）
● 使用生成式AI進行課堂即時互動（Use generative AI for real-time classroom interaction）

Note
　

Instructor	Hsiao-Chi Li　Office Hours
Email	hcli@mail.ntut.edu.tw
Last Updated	2026-06-11 09:03:57
Course Objective	本課程涵蓋以下主題： 1.數字的進制轉換以及二進制表示方式 2.布林代數式與函數 3.數位電路化簡技巧，如卡諾圖與製表法 4.組合邏輯電路，如：加法器/減法器、比較器、多工器、邊/解碼器 5.可編程邏輯電路，如：唯讀記憶體/可編程唯讀記憶體（ROM / PROM）、可編程邏輯電路（PLD）、可編程邏輯陣列（PLA） 6.順序邏輯電路，如：狀態機 Introduce the principles of digital logic. Topics includes: 1. Number representation, number bases and base conversions, and binary codes 2. Boolean algebra and functions 3. Combinational design techniques: K-maps, tabulation method 4. Combinational logic circuits: adders/subtractors, comparators, multiplexors/demultiplexers, and decoders/encoders 5. Programmable logic circuits: read-only memory/programmable read-only memory (ROM/PROM), programmable logic devices (PLD), and programmable logic arrays (PLA) 6. Sequential logic circuits: state machine
Course Schedule	Week 1: Introduction Week 2-3: Boolean Algebra & Logic Gates Week 4: Minterm & Maxterm expansions Week 5-6: Karnaugh Maps Week 7-8: Quine-McClusky Method, Multi-Level Gate Circuits (1) Week 9: Midterm Exam Week 10: Multi-Level Gate Circuits (2) Week 11: Combinational Circuit Design and Simulation Using Gates Week 12-13: Multiplexers, Decoders, and Programmable Logic Devices Week 14-15: Latches and Flip-Flops Week 16: Registers and Counters, Analysis of Clocked Sequential Circuits Week 17: Derivation of State Graphs and Tables Week 18: Final Exam
Evaluation and grading policy	Homework + Quiz 30% Midterm 30% Final 30% Attendance 10%
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:Yes Charles H. Roth, Jr. and Larry L. Kinney, Fundamentals of Logic Design, Cengage, 7th Edition, 2013..
The access to curricular consultation	Email: hcli@mail.ntut.edu.tw Office hour: Tues & Weds 10:00 ~ 12:00 or by appointment
Expanding teaching and resources	● 數位科技融入 (Digital Technology Integration) 運用生成式AI、VR/AR、IoT、IRS等新興科技輔助教學與評量。 Utilizes emerging technologies such as Generative AI, VR/AR, IoT, and IRS (Interactive Response Systems) to facilitate teaching and assessment.
The course corresponds to the SDGs	SDG4：優質教育（Quality Education） SDG9：產業創新與基礎設施（Industry, Innovation and Infrastructure）
Does the course incorporate AI	● 使用生成式AI作為教學過程的輔助工具（Use generative AI tools as an aid to the teaching process） ● 鼓勵學生使用生成式AI工具（Encourage students to use generative AI tools） ● 使用生成式AI進行課堂即時互動（Use generative AI for real-time classroom interaction）
Note