Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Spring Semester
Year 2026 355467 Digital Logic Design Experiments 1 1.0 3 ▲ Chao-Cheng Wu 4EE1C 48 0 　

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Spring Semester Year 2026	355467	Digital Logic Design Experiments	1	1.0	3	▲	Chao-Cheng Wu	4EE1C	48	0

Course Plan：

Instructor Chao-Cheng Wu　Office Hours

Email ccwu@ntut.edu.tw

Last Updated 2025-12-12 11:00:18

Course Objective This course aims to study the basis of digital circuit design. The course will begin with number systems and the Boolean algebra. Then, the binary logic gates and the minimization methods, such as Karnaugh Maps and Quine-McCluskey Method will be introduced. Afterwards, we will study combinational circuits such as Adder/Subtractor, Multiplexers, Decoders, and other Programmable Logic Devices. This will be followed by the sequential circuits: latches and flops. Registers and Counters will then be covered. The course will conclude the basic digital design techniques and various topics, including sequential circuit design techniques, state graphs, and future trends.

Course Schedule 第 1 週(2/17): 開學課程及相關規定說明第 2 週(2/24): Digital & Quartus II 簡介及使用第 3 週(3/3): 全加減法器第 4 週(3/10): 七段解碼、Decoder 第 5 週(3/17): MUX、ROM、VHDL (I) 第 6 週(3/24): VHDL (II) 第 7 週(3/31): 栓鎖器、正反器第 8 週(4/7): 暫存器、移位暫存器、靜態記憶體第 9 週(4/14): 期中考週第 10 週(4/21): 計數器、狀態機第 11 週(4/28): Moore、Mealy狀態機設計第 12 週(5/5): Reduction of State Tables and Assignments、Serial Adder 第 13 週(5/12): Equivalent State Assignments、Parallel Multiplier 第 14 週(5/19): 除法器、骰子遊戲第 15 週(5/26): 期末專題實作(I) 第 16 週(6/2): 期末專題實作(II) 第 17 週(6/9): 期末專題實作(III) 第 18 週(6/16): 期末專題實作(IV) (期末考週)

Evaluation and grading policy 1. 實作完成-含每週實習實作及作業 (60 %)、 2. 期末專題製作報告 (40 %)。

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:Yes
Fundamentals of Logic Design, 7th Edition, by Charles H. Roth, Jr. & Larry L. Kinney, Cengage, 2013.

The access to curricular consultation 課程諮商可以透過Googfle Classroom、Email(ccwu@ntut.edu.tw)另行預約時間

Expanding teaching and resources

The course corresponds to the SDGs 無（None）

Does the course incorporate AI ● 無（None）

Note
　

Instructor	Chao-Cheng Wu　Office Hours
Email	ccwu@ntut.edu.tw
Last Updated	2025-12-12 11:00:18
Course Objective	This course aims to study the basis of digital circuit design. The course will begin with number systems and the Boolean algebra. Then, the binary logic gates and the minimization methods, such as Karnaugh Maps and Quine-McCluskey Method will be introduced. Afterwards, we will study combinational circuits such as Adder/Subtractor, Multiplexers, Decoders, and other Programmable Logic Devices. This will be followed by the sequential circuits: latches and flops. Registers and Counters will then be covered. The course will conclude the basic digital design techniques and various topics, including sequential circuit design techniques, state graphs, and future trends.
Course Schedule	第 1 週(2/17): 開學課程及相關規定說明第 2 週(2/24): Digital & Quartus II 簡介及使用第 3 週(3/3): 全加減法器第 4 週(3/10): 七段解碼、Decoder 第 5 週(3/17): MUX、ROM、VHDL (I) 第 6 週(3/24): VHDL (II) 第 7 週(3/31): 栓鎖器、正反器第 8 週(4/7): 暫存器、移位暫存器、靜態記憶體第 9 週(4/14): 期中考週第 10 週(4/21): 計數器、狀態機第 11 週(4/28): Moore、Mealy狀態機設計第 12 週(5/5): Reduction of State Tables and Assignments、Serial Adder 第 13 週(5/12): Equivalent State Assignments、Parallel Multiplier 第 14 週(5/19): 除法器、骰子遊戲第 15 週(5/26): 期末專題實作(I) 第 16 週(6/2): 期末專題實作(II) 第 17 週(6/9): 期末專題實作(III) 第 18 週(6/16): 期末專題實作(IV) (期末考週)
Evaluation and grading policy	1. 實作完成-含每週實習實作及作業 (60 %)、 2. 期末專題製作報告 (40 %)。
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:Yes Fundamentals of Logic Design, 7th Edition, by Charles H. Roth, Jr. & Larry L. Kinney, Cengage, 2013.
The access to curricular consultation	課程諮商可以透過Googfle Classroom、Email(ccwu@ntut.edu.tw)另行預約時間
Expanding teaching and resources
The course corresponds to the SDGs	無（None）
Does the course incorporate AI	● 無（None）
Note