Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Fall Semester
Year 2025 348725 Digital Logic Design 1 3.0 3 ▲ Chao-Cheng Wu 4EE1C 50 3 　

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Fall Semester Year 2025	348725	Digital Logic Design	1	3.0	3	▲	Chao-Cheng Wu	4EE1C	50	3

Course Plan：

Instructor Chao-Cheng Wu　Office Hours

Email ccwu@ntut.edu.tw

Last Updated 2025-09-08 11:07:39

Course Objective 布林代數與邏輯閘，組合邏輯，算術演算邏輯，同步循序邏輯，演繹狀態機，非同步循序邏輯。

Course Schedule Week 1(9/9、11). Introduction Week 2(9/16、18). Number systems、Holiday Week 3(9/23、25). Boolean Algebra (I) Week 4(9/30、10/2). Boolean Algebra (II) & Applications of Boolean algebra minterm and maxterm expansions (I) Week 5(10/7、9). Holiday; Applications of Boolean algebra minterm and maxterm expansions (II) Week 6(10/14、16). Karnaugh Maps (I) Week 7(10/21、23). Karnaugh Maps (II) Week 8(10/28、30). Quine-McClusky Method Week 9(11/6). Midterm Exam Week 10(11/11、13). Leave for a conference Week 11(11/18、20). Multi-Level Gate Circuits NAND and NOR Gates Week 12(11/25、27). Combinational Circuit Design and Simulation Using Gates Week 13(12/2、4). Multiplexers, Decoders, and Programmable Logic Devices Week 14(12/9、11). Latches and Flip-Flops Week 15(12/16、18). Registers and Counters Week 16(12/23、25). State Machines (I) Week 17(12/30、1/1). State Machines (II) Week 18(1/8). Final Exam

Evaluation and grading policy Homework exams: 30% Circuit Design: 10% Midterm: 30% Final exam: 30% Attendance: -1% for each absence recorded Bonus (if available): 10% Total: 110%

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:Yes
Fundamentals of Logic Design Enhanced, 7th Edition, by Charles H. Roth, Jr. , Larry L. Kinney , Eugene B. John, Pearson FT Press, 2020

The access to curricular consultation 約課後時間進行諮詢

Expanding teaching and resources

The course corresponds to the SDGs 無（None）

Does the course incorporate AI ● 無（None）

Note
　

Instructor	Chao-Cheng Wu　Office Hours
Email	ccwu@ntut.edu.tw
Last Updated	2025-09-08 11:07:39
Course Objective	布林代數與邏輯閘，組合邏輯，算術演算邏輯，同步循序邏輯，演繹狀態機，非同步循序邏輯。
Course Schedule	Week 1(9/9、11). Introduction Week 2(9/16、18). Number systems、Holiday Week 3(9/23、25). Boolean Algebra (I) Week 4(9/30、10/2). Boolean Algebra (II) & Applications of Boolean algebra minterm and maxterm expansions (I) Week 5(10/7、9). Holiday; Applications of Boolean algebra minterm and maxterm expansions (II) Week 6(10/14、16). Karnaugh Maps (I) Week 7(10/21、23). Karnaugh Maps (II) Week 8(10/28、30). Quine-McClusky Method Week 9(11/6). Midterm Exam Week 10(11/11、13). Leave for a conference Week 11(11/18、20). Multi-Level Gate Circuits NAND and NOR Gates Week 12(11/25、27). Combinational Circuit Design and Simulation Using Gates Week 13(12/2、4). Multiplexers, Decoders, and Programmable Logic Devices Week 14(12/9、11). Latches and Flip-Flops Week 15(12/16、18). Registers and Counters Week 16(12/23、25). State Machines (I) Week 17(12/30、1/1). State Machines (II) Week 18(1/8). Final Exam
Evaluation and grading policy	Homework exams: 30% Circuit Design: 10% Midterm: 30% Final exam: 30% Attendance: -1% for each absence recorded Bonus (if available): 10% Total: 110%
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:Yes Fundamentals of Logic Design Enhanced, 7th Edition, by Charles H. Roth, Jr. , Larry L. Kinney , Eugene B. John, Pearson FT Press, 2020
The access to curricular consultation	約課後時間進行諮詢
Expanding teaching and resources
The course corresponds to the SDGs	無（None）
Does the course incorporate AI	● 無（None）
Note