Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Spring Semester
Year 2026 355037 Electronic Lab. (II) 1 1.0 3 ▲ YU-CHENG FAN 4EN2A 64 0 　

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Spring Semester Year 2026	355037	Electronic Lab. (II)	1	1.0	3	▲	YU-CHENG FAN	4EN2A	64	0

Course Plan：

Instructor YU-CHENG FAN　Office Hours

Email skystar@ntut.edu.tw

Last Updated 2025-12-15 21:06:28

Course Objective 內容包含：1. 數位電子平台簡介(NC Verilog, Logic Synthesis, DFT, APR, Custom-Sim); 2. NC Verilog to Logic Synthesis; 3. Logic Synthesis with Design Compiler; 4. Adder Design (NC Verilog + Design Compiler); 5. Block Level Design (NC Verilog+Design Compiler+TSMC Process); 6. CHIP Level Design Using TSMC Process; 7. Retiming (NC Verilog+Design Compiler); 8. Design for Testability with DFT Compiler and TetraMAX; 9. Auto Placement & Routing with Innovus; 10. Server 環境操作，11. Schematic 的使用，12. Spectre 的使用，13. Inverter simulation，14. Oscillator simulation，15. VCO simulation，16. OP simulation

Course Schedule 1 數位電子平台簡介(NC Verilog, Logic Synthesis, DFT, APR, Custom-Sim) 2 數位電路實驗(1) NC Verilog to Logic Synthesis 3 數位電路實驗(2) Logic Synthesis with Design Compiler 4 數位電路實驗(3) Adder Design (NC Verilog + Design Compiler) 5 數位電路實驗(4) Block Level Design (NC Verilog+Design Compiler+TSMC Process) 6 數位電路實驗(5) CHIP Level Design Using TSMC Process 7 數位電路實驗(6) Retiming (NC Verilog+Design Compiler) 8 數位電路實驗(7) Design for Testability with DFT Compiler and TetraMAX 9 數位電路實驗(8) Auto Placement & Routing with Innovus 10 Server 環境操作 11 Schematic 的使用 12 Spectre 的使用 13 Inverter simulation 14 Oscillator simulation 15 VCO simulation 16 OP simulation(I) 17 OP simulation(II) 18 期末測驗

Evaluation and grading policy 數位實驗分數 50% 類比實驗分數 50%

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:No
教師自編講義

The access to curricular consultation Office Hours: Mon. 345678
溝通管道(E-mail: skystar@ntut.edu.tw)

Expanding teaching and resources

The course corresponds to the SDGs SDG1：消除貧窮（No Poverty）
SDG4：優質教育（Quality Education）
SDG9：產業創新與基礎設施（Industry, Innovation and Infrastructure）
SDG11：永續城市與社區（Sustainable Cities and Communities）
SDG12：負責任的消費與生產（Responsible Consumption and Production）
SDG17：夥伴關係（Partnerships for the Goals）

Does the course incorporate AI ● 鼓勵學生使用生成式AI工具（Encourage students to use generative AI tools）

Note
溝通管道(E-mail: skystar@ntut.edu.tw)

Instructor	YU-CHENG FAN　Office Hours
Email	skystar@ntut.edu.tw
Last Updated	2025-12-15 21:06:28
Course Objective	內容包含：1. 數位電子平台簡介(NC Verilog, Logic Synthesis, DFT, APR, Custom-Sim); 2. NC Verilog to Logic Synthesis; 3. Logic Synthesis with Design Compiler; 4. Adder Design (NC Verilog + Design Compiler); 5. Block Level Design (NC Verilog+Design Compiler+TSMC Process); 6. CHIP Level Design Using TSMC Process; 7. Retiming (NC Verilog+Design Compiler); 8. Design for Testability with DFT Compiler and TetraMAX; 9. Auto Placement & Routing with Innovus; 10. Server 環境操作，11. Schematic 的使用，12. Spectre 的使用，13. Inverter simulation，14. Oscillator simulation，15. VCO simulation，16. OP simulation
Course Schedule	1 數位電子平台簡介(NC Verilog, Logic Synthesis, DFT, APR, Custom-Sim) 2 數位電路實驗(1) NC Verilog to Logic Synthesis 3 數位電路實驗(2) Logic Synthesis with Design Compiler 4 數位電路實驗(3) Adder Design (NC Verilog + Design Compiler) 5 數位電路實驗(4) Block Level Design (NC Verilog+Design Compiler+TSMC Process) 6 數位電路實驗(5) CHIP Level Design Using TSMC Process 7 數位電路實驗(6) Retiming (NC Verilog+Design Compiler) 8 數位電路實驗(7) Design for Testability with DFT Compiler and TetraMAX 9 數位電路實驗(8) Auto Placement & Routing with Innovus 10 Server 環境操作 11 Schematic 的使用 12 Spectre 的使用 13 Inverter simulation 14 Oscillator simulation 15 VCO simulation 16 OP simulation(I) 17 OP simulation(II) 18 期末測驗
Evaluation and grading policy	數位實驗分數 50% 類比實驗分數 50%
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:No 教師自編講義
The access to curricular consultation	Office Hours: Mon. 345678 溝通管道(E-mail: skystar@ntut.edu.tw)
Expanding teaching and resources
The course corresponds to the SDGs	SDG1：消除貧窮（No Poverty） SDG4：優質教育（Quality Education） SDG9：產業創新與基礎設施（Industry, Innovation and Infrastructure） SDG11：永續城市與社區（Sustainable Cities and Communities） SDG12：負責任的消費與生產（Responsible Consumption and Production） SDG17：夥伴關係（Partnerships for the Goals）
Does the course incorporate AI	● 鼓勵學生使用生成式AI工具（Encourage students to use generative AI tools）
Note	溝通管道(E-mail: skystar@ntut.edu.tw)