Course Syllabus

Course Information：

Year-Semester Course Number Course Name Phase Credits Hours Required/Elective Instructor Class Student NO. Withdraw Note

Spring Semester
Year 2025 341756 Digital Logic Design Lab. 1 1.0 3 ▲ SHINGCHERN YOU 4CSIE1 70 0 科1222(週五)

Year-Semester	Course Number	Course Name	Phase	Credits	Hours	Required/Elective	Instructor	Class	Student NO.	Withdraw	Note
Spring Semester Year 2025	341756	Digital Logic Design Lab.	1	1.0	3	▲	SHINGCHERN YOU	4CSIE1	70	0	科1222(週五)

Course Plan：

Instructor SHINGCHERN YOU　Office Hours

Email scyou@ntut.edu.tw

Last Updated 2024-12-17 17:03:26

Course Objective １.TTL，CMOS邏輯閘之特性實習２.組合邏輯電路設計實習３.序向邏輯電路設計與應用４.FPGA設計規劃。

Course Schedule Week 1 General Announcement and Lab Administration Week 2 Holiday Week 3 Lab 0: Use of Lab equipment Week 4 Lab 1: Characteristics of logic gates Week 5 Lab 2: Modified Linear Decoder Week 6 Lab 3: FPGA Combinational Circuits (1) Week 7 Holiday Week 8 Lab 3: FPGA Combinational Circuits (2) Week 9 Lab 4: Multivibrator Circuits Week 10 Lab 5: Simple Traffic Controller (1) Week 11 Lab 5: Simple Traffic Controller (2) Week 12 Lab 6: Serial Data Transmissions (1) Week 13 Lab 6: Serial Data Transmissions (2) Week 14 Lab 7: FPGA Sequential Circuits (1) Week 15 Holiday Week 16 Lab 7: FPGA Sequential Circuits (2) Week 17 Final exam

Evaluation and grading policy Participation and check off worked circuits: 60% Lab reports: 20 % Final exam: 20 % (*) * The final exam covers basic knowledge students should know to successfully complete the lab experiments. Students whose final exam scores below 33 points are determined not to have enough knowledge to complete the experiments independently. Therefore, the instructor reserves the rights not to count the points of some worked circuits and reports for those students.

Materials All right reserved. Do not reproduce without permission.

Foreign-language textbooks:No
Lecture notes and reference datasheets are available as handouts.

The access to curricular consultation 我的研究室: 科研大樓1533
我的email：scyou@ntut.edu.tw。

Expanding teaching and resources

The course corresponds to the SDGs 無（None）

Does the course incorporate AI

Note
若學校因應疫情規定遠距教學，則使用Microsoft Teams平台上課
1. 學校的 Microsoft Teams 使用（學號@cc.ntut.edu.tw）登入
2. 我的email：scyou@ntut.edu.tw。

Instructor	SHINGCHERN YOU　Office Hours
Email	scyou@ntut.edu.tw
Last Updated	2024-12-17 17:03:26
Course Objective	１.TTL，CMOS邏輯閘之特性實習２.組合邏輯電路設計實習３.序向邏輯電路設計與應用４.FPGA設計規劃。
Course Schedule	Week 1 General Announcement and Lab Administration Week 2 Holiday Week 3 Lab 0: Use of Lab equipment Week 4 Lab 1: Characteristics of logic gates Week 5 Lab 2: Modified Linear Decoder Week 6 Lab 3: FPGA Combinational Circuits (1) Week 7 Holiday Week 8 Lab 3: FPGA Combinational Circuits (2) Week 9 Lab 4: Multivibrator Circuits Week 10 Lab 5: Simple Traffic Controller (1) Week 11 Lab 5: Simple Traffic Controller (2) Week 12 Lab 6: Serial Data Transmissions (1) Week 13 Lab 6: Serial Data Transmissions (2) Week 14 Lab 7: FPGA Sequential Circuits (1) Week 15 Holiday Week 16 Lab 7: FPGA Sequential Circuits (2) Week 17 Final exam
Evaluation and grading policy	Participation and check off worked circuits: 60% Lab reports: 20 % Final exam: 20 % () The final exam covers basic knowledge students should know to successfully complete the lab experiments. Students whose final exam scores below 33 points are determined not to have enough knowledge to complete the experiments independently. Therefore, the instructor reserves the rights not to count the points of some worked circuits and reports for those students.
Materials	All right reserved. Do not reproduce without permission. Foreign-language textbooks:No Lecture notes and reference datasheets are available as handouts.
The access to curricular consultation	我的研究室: 科研大樓1533 我的email：scyou@ntut.edu.tw。
Expanding teaching and resources
The course corresponds to the SDGs	無（None）
Does the course incorporate AI
Note	若學校因應疫情規定遠距教學，則使用Microsoft Teams平台上課 1. 學校的 Microsoft Teams 使用（學號@cc.ntut.edu.tw）登入 2. 我的email：scyou@ntut.edu.tw。