| Description
| 1. Design Flow Overview
2. RTL Design in Verilog
3. Basic placement & routing
4. Post Layout Simulation
5. LVS & DRC & ERC
6. Time-Mill and Power-Mill Post Layout Simulation
7. Module Compiler
8. Physical Compiler
9. Clock Tree Synthesis, Zero Skew Routing
10. Scan Chain Optimization/Reordering
11. Constraint driven placement &routing (timing, power, heat)
12. Buffer/wire sizing
13. Cell library creation (layout, simulation model, parameter extraction, synthesis model)
14. Verilog code design
15. Pre_simulation
16. LVS & DRC & ERC Flow
17. Time-Mill and Power-Mill Post Layout Simulation Flow
18. Design examples
19. Placement &routing flow
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