| Description
| Discuss the theorems and techniques of the Digital Circuit Testing and Design for Testability(DFT). Introduces Failures and Faults, Modeling of Fault.Describes Automatic Test Patterm Generation techniques which include Boolean Difference, D-Algorithm, PODEM (Path-Oriented Decision-Marking), FAN(Fanout-Oriented Test Generation) and Critical Path. Introduces Fault Simulation methods like Parallel Fault Simulation, Deductive Fault Simulation and oncurrent Fault Simluation. Presents the basic concepts and main techniques used in Design for Testability are Ad Hoc techniques, Scan Path Design, LSSD(Level-Sensitive Scan Design) techniques, Boundary Scan with IEEE 1149.1 Standard and BIST(Built-in Self-Test).
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