教學大綱與進度

課程基本資料：

學年期	課號	課程名稱	階段	學分	時數	修	教師	班級	人	撤	備註
106-2	237639	數位系統設計	1	3.0	3	★	陳雲潮	電子三甲 電子三乙 資工三	26	5	電子大三日夜與資工三合開

教學大綱與進度：

教師姓名	陳雲潮
Email	mikechen@ieee.org
最後更新時間	2018-03-06 10:43:29
課程大綱	1. Concurrent Code 2. Sequential Code 3. Signal and Variable 4. Package and Component 5. Simulation with Testbench 6. Design of State Machines 7. Design of Altera Qsys and NIOS-SoC 8. Serial Parallel Multiplier System 9. Parallel Multiplier System 10. Multiply-Accumulate System 11. FIR Digital Filter 12. Introduction to Neural Networks
課程進度	Week- 1 No Class (2/28) Week- 2 Introduction to Digital System Design (3/7) Week- 3 Concurrent Code and Devices Design (2/14) Week- 4 Simulation with VHDL Testbench (3/21) Week- 5 Testing with Pattern Generator and Digital Analyzer (3/28) Week- 6 No Class (4/4) Week- 7 Sequential Code and Devices Design (4/11) Week- 8 Signal and Variables (4/18 ) Week- 9 Mid Term Test (4/25) Week- 10 Package and Component for System design (5/2) Week- 11 Function and Procedure in System Design (5/9) Week- 12 Design with State Machines (5/16) Week- 13 Design of Altera Qsys and NIOS-SoC (5/23) Week- 14 Serial Parallel Multiplier System (5/30) Week- 15 Parallel Multiplier System (6/6) Week- 16 Multiply-Accumulate System (6/13) Week- 17 FIR Digital Filter (6/20) Week- 18 Final Test (6/21)
評量方式與標準	1. Two Quizes 20% 2. Mid term test 20% 3. Final test 20% 4. Home works 40%
使用教材、參考書目或其他	【遵守智慧財產權觀念，請使用正版教科書，不得使用非法影印教科書】 使用外文原文書：是 1. Text Book: Circuit Design and Simulation with VHDL 2nd Edition Volnei A.pedroni / The MIT Press 2010 2. Reference Book: Finite State Machine in Hardware Volnei A.pedroni / The MIT Press 2013 3. Reference Book: Digital System Design Using Verilog Charles Roth / CENGAGE Learning 2016 4. Lab Book: iLAB-FPGA 數位系統設計摸擬測試與硬體除錯 陳雲潮 / 東華書局 2016
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