教學大綱與進度
課程基本資料:
學年期
課號
課程名稱
階段
學分
時數
修
教師
班級
人
撤
備註
99-1
137548
數位邏輯
1
3.0
3
▲
吳昭正
四電一乙
54
0
教學大綱與進度:
教師姓名
吳昭正
Email
ccwu@ntut.edu.tw
最後更新時間
2010-08-30 15:47:53
課程大綱
This course covers the following topics: 1. Number systems and conversion 2. Boolean algebra 3. Simplification of Boolean algebra 4. Gate Circuits 5. Combinational Circuit Design 6. Flip-Flops, Registers, and Counters 7. Introduction to VHDL 8. Sequential Circuits 9. State Graphs and Tables
課程進度
Week 1. Introduction Week 2. Boolean Algebra & Logical Gates (I) Week 3. Boolean Algebra & Logical Gates (II) Week 4. Minterm and Maxterm Expansions Week 5. Karnaugh Maps Week 6. Quine-McClusky Method Week 7. Multi-Level Gate Circuits Week 8. Combinational Circuit Design and Simulation Using Gates (I) Week 9. Midterm Exam Week 10. Combinational Circuit Design and Simulation Using Gates (II) Week 11. Multiplexers, Decoders, and Programmable Logic Devices Week 12. Introduction to VHDL Week 13. Latches and Flip-Flops Week 14. Registers and Counters Week 15. Analysis of Clocked Sequential Circuits Week 16. Derivation of State Graphs and Tables Week 17. Sequential Circuit Design Week 18. Final Exam
評量方式與標準
Homework 20% Midterm 30% Final 40% Attendance 10%
使用教材、參考書目或其他
【遵守智慧財產權觀念,請使用正版教科書,不得使用非法影印教科書】
使用外文原文書:
Textbook: Fundamentals of Logic Design, 6th Edition, by Charles H. Roth, Jr. & Larry L. Kinney, Cengage, 2010
課程諮詢管道
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