| 課程編碼 Course Code | 中文課程名稱 Course Name (Chinese) | 英文課程名稱 Course Name (English) | 總學分數 Credits | 總時數 Hours |
|---|---|---|---|---|
| 3604103 | 數位積體電路後段設計 | Digital integrated circuit back-end design | 3.0 | 3 |
| 中文概述 Chinese Description | 此課程之目標為前瞻性數位積體電路後段設計流程整合實務, 可訓練學生熟悉使用晶片設計流程, 以完成晶片後段設計之實務。 課程內容包含: 1. Design Flow Overview 2. RTL Design in Verilog 3. Basic placement & routing 4. Post Layout Simulation 5. LVS & DRC & ERC 6. Time-Mill and Power-Mill Post Layout Simulation 7. Module Compiler 8. Physical Compiler 9. Clock Tree Synthesis, Zero Skew Routing 10. Scan Chain Optimization/Reordering 11. Constraint driven placement &routing 12. Buffer/wire sizing 13. Cell library creation 14. Verilog code design 15. Pre_simulation 16. LVS & DRC & ERC Flow 17. Time-Mill and Power-Mill Post Layout Simulation Flow 18. Design examples 19. placement &routing flow | |||
| 英文概述 English Description | This course is trained the student to understand back-end IC design flow. Therefore, the student has the design capability of advanced IC. The contents of this course: 1. Design Flow Overview 2. RTL Design in Verilog 3. Basic placement & routing 4. Post Layout Simulation 5. LVS & DRC & ERC 6. Time-Mill and Power-Mill Post Layout Simulation 7. Module Compiler 8. Physical Compiler 9. Clock Tree Synthesis, Zero Skew Routing 10. Scan Chain Optimization/Reordering 11. Constraint driven placement &routing 12. Buffer/wire sizing 13. Cell library creation 14. Verilog code design 15. Pre_simulation 16. LVS & DRC & ERC Flow 17. Time-Mill and Power-Mill Post Layout Simulation Flow 18. Design examples 19. placement &routing flow | |||
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